This invention relates to a transistor switch assembly, and more particularly to such a switch assembly having reduced parasitic inductance.
Transistor switches are widely used in power circuits for controlling the flow of power to a load. For example, a conventional three-phase inverter includes transistor switches for converting a direct current input to a three-phase AC power supply. Such an inverter includes six building blocks or modules, the blocks being arranged in three pairs (see FIG. 1 herein which will be discussed later) connected across the DC input. Each block includes a switch transistor and an antiparallel diode connected across it. During operation of the circuit, parasitic inductance in the wiring between the blocks of a pair results in undesirable voltage peaks across the transistor of each block at the instant of switching. These peaks may be accommodated by increasing the size and weight of a transistor snubber circuit connected in parallel with the transistor, but a more advantageous solution would be to substantially reduce the undesirable parasitic inductance.
Nishihiro et al. U.S. Pat. No. 4,816,981, and Porst et al. U.S. Pat. No. 4,816,984 show circuits including inverters. The Nishihiro patent shows building blocks as discussed above, and the Porst patent shows circuits and physical layouts of the components for reducing the effects of voltage peaks which occur during switching.
It is a general object of the present invention to provide an improved circuit which overcomes the disadvantages of the prior art.